1. Field of the Invention
The invention relates to a write speed-up circuit for integrated data memories and more particularly to a speed-up circuit for use with cross-coupled, bipolar transistor storage cells.
2. Description of the Prior Art
Storage cells of cross coupled bipolar transistors are described in commonly assigned U.S. Pat. No. 3,505,573 and in U.S. Pat. No. 3,693,057. The operation of such a cross coupled bipolar storage cell is described in detail in the first-mentioned patent. In such a storage cell one transistor is always conductive while the other is non-conductive. In stand-by, the current flows through the conductive transistor whose emitter is at a potential of 0 Volt. When addressing, the emitter of the conductive transistor is rendered non-conductive, and a current flows via the emitter resistor whose voltage drop is detected as a read pulse. When information is written into the storage cell the conductive transistor, upon the application of an addressing pulse to its emitter, is cut off. The diodes which are arranged in parallel to the two collector resistors effect a high current switching upon the addressing. In stand-by, these two diodes are off, whereas upon addressing the diode of the conductive collector branch becomes conductive, and thus a relatively low resistance is arranged in parallel to the conductive collector resistor. If several such storage cells are provided in a word-organized memory, the word selection is performed by means of decreasing the word line potential by about 1 V relative to the potential of the unselected word lines in the memory. From the selected word, bits are selected by driving both bit lines, and writing is achieved by driving only one bit line. Such cells, because of inherent capacitance in the cells, require relatively long write times, high write currents, and consequently require higher power.